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Quad E1 Transceiver Chip |
| OVERVIEW |
| Quad E1 Transceiver CP5024 is one of the ETLINK series chips designed by Chiphomer Technology Company, it integrates four independent E1 transceivers into a single chip. Each E1 transceiver works functionally as CP5021, which provide complete function of E1 line interface and E1 Framer. |
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| FEATURES |
• Quad complete E1 (CEPT) PCM-30 /ISDN-PRI transceiver functionality
• Short haul line interface for clock/data recovery and wave shaping
• 32-bit or 64-bit crystal-less jitter attenuator
• E1 Framers supporting framed or unframed data receive and transmit
• Frames FAS, CAS, CCS and CRC4 formats
• Dual 512-bit elastic buffers respectively for receive and transmit direction, controlled slip capability and slip indication
• Supports Sa and Si bits insertion and extraction
• Detects and generates Receive Carrier Loss (RCL), Synchronization Loss (RLOS),AIS, remote alarm, and remote multi-frame alarms
• Inserts and extracts CAS signaling,
• Integrated HDLC controller with two 64-byte buffers configurable for Sa bit and sub DS0 operation
• Provides three types of loop-back for system testing purpose
• 8 bit parallel microprocessor interface supports either multiplexed or non-multiplexed bus with Intel or Motorola mode
• Large counters for Bipolar and code violations, CRC4 code word errors, FAS word errors, and E bits
• IEEE 1149.1 JTAG-Boundary Scan Architecture
• CMOS 3.3 V technology£¬3.3V CMOS level with 5V tolerant for I/O pads
• Low power consumption
• Operating Temperature Range: -40”ę ~ 85”ę
• LQFP-100 package |
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| APPLICATIONS |
• PBX
• Digital Access Cross Connect Systems (DACS)
• SONET/SDH Add/Drop Multiplexer
• VoIP Gateways, Multiplexer |
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LQFP-100
-40 oC ~ 85 oC |
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| TYPICAL APPLICATION |
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